Material Selection

Material selection is a crucial design parameter to get the most out of your electrical signal without incurring higher costs.

Also, not all materials have a robust Asian supply chain. Working with your PCB vendor during design can help reduce material delivery and build start delays.

Common material applications include:
  • High-Td FR4 for RoHS-compliant lead-free assembly and dimensional stability (Ex: IT-180A, S1000-2, EM-827, & 370HR)
  • Low loss, high speed digital (Ex: FR408, N-13EP, TU-872 SLK, & Meg4)
  • Halogen Free (Ex: EM-285, IT-150G, S1165, & TU-862 HF)
  • RF or RF/digital hybrid materials (Ex: Meg6, 4350B, & 4350B core w/ FR4 buildup)
  • Flex (FPC) and flex-rigid

Impedance

Will the board need impedance control for timing on clock or transmission lines, USB, DDR, video, or other unique device drivers?

  • Application Engineers can do impedance modeling with a 2D Field solver to help with accurate layout
  • Application Engineers can optimize stackups during layout to ensure impedance targets are met with common manufacturable constructions and lowest cost
  • TDR verification test can be performed on representative coupon during manufacturing

Via Structures

Most designs work well with standard thru vias but sometimes more advanced via structures are needed.

Discussing the design intent with an Application Engineer prior to layout will help optimize the stackup and board manufacturability while controlling costs.

Common design features that may need advanced via structures include:
  • BGA devices < 0.65mm which typically need a combination of microvias and thru vias to be manufacturable in volume with good long-term reliability
  • Blind vias may be desired for cleaner signal return paths or for real-estate challenges on small boards
  • Boards with different footprints on each side (interposer & module boards) may need to use a combination of blind and buried vias


Trace and Space

Etching fine line trace and space, especially on plated layers, can directly affect the manufacturability of the board
  • Using a larger trace and space than the minimum manufacturable (typically 3 mils trace and space min for most factories) can help control costs and increase manufacturing yields
  • Aim for 4 mils min trace/space on internal layers and 5 mils min trace/space on external layers for best manufacturability
  • Donut rings in copper pour areas are a two-fold concern: 1. Thin isolated rings of imaging resist are hard to adhere to the board during plating processes. 2. The rings have reduced etch chemistry circulation and are harder to etch clear at smaller sizes
  • Application Engineers can help pin out microBGA devices (0.65mm and smaller) and help optimize two track routing between pins on ≥1.00 mm devices

Drills and Padstacks

Drill aspect ratio (board thickness divided by the drill size) and adequate pad sizes to allow for drill registration tolerances need to be taken into the design consideration.

  • Best manufacturability is achieved when aspect ratios are < 10:1 even though many factories can accommodate higher aspect ratios with a small impact to yield
  • Industry standard is to select VIA drill sizes the same as the finished hole size (FHS) whereas component thru holes are typically drilled 5 mils over the FHS (4 mils over for press-fit technology)
  • Material movement (scaling), drill machine runout, & drill deflection all affect drill to pad accuracy when selecting padstacks
  • Drill to copper on internal layers is crucial for long-term board reliability – aim for 9 mils min drill edge to Cu for best manufacturability

Surface Finish

Work with BOTH the PCB fab vendor and the assembler to select the right surface finish
  • Common finishes are OSP, Imm Ag, ENIG, Imm Sn, HASL & lead-free HASL, and electrolytic Ni/Au
  • Each finish has pros and cons so it’s best to speak with an Application Engineer about what attributes the board has for the intended application
  • Be careful when selecting dual finishes (one for solderable pads and another for edge connectors or contact pads) as not all designs combinations can be easily manufactured

Via Treatments

Often an afterthought, via treatment selection and soldermask geometries can have an impact on both the manufacturability and long-term reliability of the vias and solder joints.

  • Decide whether a soldermask treatment will meet the end use of the via or whether a non-conductive via fill plug with over plating will be required for vias designed inside a solderable pad
  • Remember holes are three-dimensional when determining which via treatments to apply to one or both sides of the same hole
  • Most surface finishes are applied after soldermask and tented or partially-tented vias will be exposed to acid baths and neutralizing rinses during future processing
  • Tented holes without a pre-plug process are typically not robust enough to withstand chemical processing after application
  • Soldermask encroachment covers the majority of the exposed metal but allows adequate solution flow through the hole during surface finish processing

Mechanical Features


Will your board need mechanical attributes fabricated or special feature-size or positional tolerances?
  • V-score, edge bevel, countersinks, counterbores, and other special mechanical features all need to be clearly detailed on the fab drawing
  • Backdrills for signal integrity need to be designed with adequate clearances in both X/Y & Z axis
  • Pallet/array designs need adequate clearances to create mechanical features inside the array outline (example beveled gold fingers surrounded by breakaway material need a routed clearance)
  • Pull back internal planes and external Cu pour from board edges by .010” to ensure no exposed or lifting metal after final board outline routing

Thieving (External)


External thieving is primarily used to balance plating and etching distribution. Plated copper thicknesses change with the localized current density.

  • Features closer to vias and other nearby features (example BGAs and via farms) will plate similarly due to even current distribution
  • Isolated traces & holes will plate more and etch slower because there is little nearby to distribute the current with
  • Thin traces running between large holes in component arrays will plate less and etch quicker/thinner – the larger component holes use most of the current

Thieving (Internal)

Internal thieving is primarily used to balance pressure during press/lamination.

  • Large areas void of Cu on internal layers (planes or signals) are considered low pressure areas and harder to vacuum air out of these areas on the board
  • Entrapped air creates voids in the material after the lamination process is complete
  • Heavier copper weights require adjacent prepregs with more resin content and sometimes multiple plies to ensure adequate resin fill
  • Repeat open areas in the same Z-axis location of the design create even greater low pressure areas for laminate voids to develop

Positive plane layers
(white & red areas void of Cu)

Laminate Void
(viewed from surface)


Laminate Void
(crossection view)